(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming encased copper interconnects in a semiconductor substrate by using an improved damascene process.
(2) Description of the Related Art
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices in integrated circuits improves in a compounded fashion. That is, the device speed as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along the interconnects that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivities for high signal propagation. Copper is often preferred for its low resistivity, as well as for resistance to electromigration and stress voiding properties. Unfortunately, however, copper suffers from high diffusivity in common insulating materials such as silicon oxide, and oxygen-containing polymers. This can cause corrosion of the copper with the attendant serious problems of loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the circuitry. A copper diffusion barrier is therefore often required. A method of encasing copper conductors with a diffusion barrier is disclosed later in the embodiments of this invention.
Conventionally, the various metal interconnect layers in a semiconductor substrate are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate. It will be observed that patterning, that is, photolithography and etching of metal layers to form the needed interconnects constitute a significant portion of the process steps of manufacturing semiconductor substrates, and it is known that both photolithography and etching are complicated processes. It is desirable, therefore, to minimize such process steps, and dual damascene process provides such an approach. It will be shown later in the embodiments of this invention how such a dual damascene process is especially suited for forming copper interconnects.
In a single damascene process, grooves are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, the conductive hole openings are also formed in the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers.
In the standard dual damascene process an insulating layer, (20), shown in FIG. 1a, is coated with a resist material, (30), which is exposed to a first mask with the image pattern of a hole opening (35') for either a contact or via hole, and the pattern is anisotropically etched, (35), in the upper half (20b) of the insulating layer. The hole depth in the insulating layer can be controlled by timed-etch. That is, the etch is stopped after a predetermined period of time. However, timed-etch is not always reliable. In order to have a better control on the depth of the hole, an etch-stop layer is also be used, as is well known in the art. Etch-stop layer is usually a thin conformal material such as silicon nitride (Si.sub.3 N.sub.4, SiN), silicon oxynitride (SiO.sub.x N.sub.y), or titanium nitride (TiN) which have high selectivity to the etchant. Thus, hole opening (35) in layer (20) stops at etch-stop layer (25) shown in FIG. 1a. The etchant is then modified to etch the hole pattern through the etch-stop layer and stop at the insulating layer below. After etching, patterned resist material (30) is removed, insulating layer (20) is coated with another resist material (40) and exposed to a second mask with image pattern of conductive lines (45') in alignment with hole openings (35) as shown in FIG. 1b. In anisotropically etching the openings for the conductive line in the upper half of the insulating material, the hole openings already present in the upper half are simultaneously etched in the lower half (20a) of the insulating material. After the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing as shown in FIG. 1c.
In another approach for the dual damascene process, the conductive line openings, (45'), are etched first into the upper half of the insulating material, (20b), as shown in FIG. 2a, using an etch-stop layer (25). Resist material, (30), is next formed over the substrate, thus filling the line opening (45), and patterned with hole opening (35'), as shown in FIG. 2b. The hole pattern is then etched into the lower half (20a) of the insulating material, thus forming the dual damascene structure. Again, after the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing as shown in FIG. 2c.
Other similar techniques such as trenching are also used for forming electrical interconnects. Carey, in U.S. Pat. No. 5,091,339, teaches the forming of conductor channels and vias using processes such as die stamping, etching, plating and polishing. Thus, he provides an insulating layer on a base, forming a channel in the top surface and partially through the thickness of the insulating layer, forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel, depositing an electrical conductor into the channel and via, and planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conductive channel interconnected to an electrically conducting via.
Cote, et al., disclose the capping of low resistivity metal conductor lines with refractory metal in U.S. Pat. No. 5,262,354, where, first, a controlled amount of a soft, low resistivity metal is deposited in a trench or hole to a point below the top surface of the dielectric in which the trench or hole is formed. Subsequently, the low resistivity metal is overcoated with a hard metal such as CVD tungsten. Finally, chemical mechanical polishing is used to planarize the structure. According to Cote, et al., the hard metal cap serves the function of protecting the low resistivity metal from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical mechanical polishing slurries.
Krishnan, in U.S. Pat. No. 5,451,551, also discloses a multilevel metallization process using polishing along with a maskless process. Here, a first barrier layer is disposed in a recess in an insulating layer, a conductive metal is disposed on a the first barrier material such that the entire metal feature is positioned within the recess below the top of the recess, a second barrier material is disposed on the metal feature such that the second barrier material occupies the entire portion of the recess above the metal feature and extends above the top surface of the insulating layer, and the second barrier material is then polished until the top of the second barrier material is in and aligned with the top of the insulating layer. As a result, the metal feature is surrounded and protected by the first and second barrier materials, and the substrate is planarized.
Although prior art utilizes trenching or damascene techniques for forming interconnects, as well as techniques for protecting the same, especially the latter techniques are complex and complicated. For example, in U.S. Pat. No. 5,451,551, using chemical mechanical polishing to "attack and remove copper [in trenches] without removing . . . " the barrier layer from the surface of the substrate can be difficult. This is especially true when one takes into account the pattern dependency of dishing as is known in the art. Furthermore, two types of polishing slurry are required in polishing copper, and then the barrier material. Some of these problems are overcome in the present invention as disclosed below.